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HPCA
2012
IEEE

BulkSMT: Designing SMT processors for atomic-block execution

11 years 11 months ago
BulkSMT: Designing SMT processors for atomic-block execution
Multiprocessor architectures that continuously execute atomic blocks (or chunks) of instructions can improve performance and software productivity. However, all of the prior proposals for such architectures assume single-context cores as building blocks — rather than the widely-used Simultaneous Multithreading (SMT) cores. As a result, they are underutilizing hardware resources. This paper presents the first SMT design that supports continuous chunked (or transactional) execution of its contexts. Our design, called BulkSMT, can be used either in a single-core processor or in a multicore of SMTs. We present a set of BulkSMT configurations with different cost and performance. We also describe the architectural primitives that enable chunked execution in an SMT core and in a multicore of SMTs. Our results, based on simulations of SPLASH-2 and PARSEC codes, show that BulkSMT supports chunked execution cost-effectively. In a 4-core multicore with eager chunked execution, BulkSMT reduce...
Xuehai Qian, Benjamin Sahelices, Josep Torrellas
Added 24 Apr 2012
Updated 24 Apr 2012
Type Journal
Year 2012
Where HPCA
Authors Xuehai Qian, Benjamin Sahelices, Josep Torrellas
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