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VLSID
2009
IEEE

Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems

14 years 4 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a novel six-transistor (6T) SE-SRAM bitcell for low-Vdd and highspeed embedded applications with significant improvement in their power, performance and stability under process variations. The proposed design has a strong 2.65? worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic `one' is achieved, which is problematic in SE-SRAM cells even at lower voltage. The proposed bitcell design is mainly targeted for word-organized SRAMs. A 16 ? 16 ? 32 bit SRAM with proposed and standard 6T bitcells is simulated (including parasitics) for 65nm CMOS technology to evaluate and compare the different performance parameters, such as, read SNM, write-ability, access delay and power. The dynamic and leakage power dissipation in the proposed 6T design is reduced by 28% ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi
Added 23 Nov 2009
Updated 23 Nov 2009
Type Conference
Year 2009
Where VLSID
Authors Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan
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