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HPCA
2009
IEEE

iCFP: Tolerating all-level cache misses in in-order processors

14 years 4 months ago
iCFP: Tolerating all-level cache misses in in-order processors
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow freely around data cache misses. As a result, they have difficulties overlapping independent misses with one another. Previously proposed techniques like Runahead execution and Multipass pipelining have attacked this problem. In this paper, we go a step further and introduce iCFP (in-order Continual Flow Pipeline), an adaptation of the CFP concept to an in-order processor. When iCFP encounters a primary data cache or L2 miss, it checkpoints the register file and transitions into an "advance" execution mode. Miss-independent instructions execute as usual and even update register state. Missdependent instructions are diverted into a slice buffer, un-blocking the pipeline latches. When the miss returns, iCFP "rallies" and executes the contents of the slice buffer, merging miss-dependent stat...
Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
Added 25 Nov 2009
Updated 25 Nov 2009
Type Conference
Year 2009
Where HPCA
Authors Andrew D. Hilton, Santosh Nagarakatte, Amir Roth
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