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DATE
2009
IEEE

Optimizing data flow graphs to minimize hardware implementation

13 years 10 months ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common subexpression elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor Expansion Diagram. The method is generic, applicable to arbitrary algebraic expressions and does not require specific knowledge of the application domain. Experimental results show that the DFGs generated from such optimized expressions are better suited for high level synthesis, and the final, scheduled implementations are characterized, on average, by 15.5% lower latency and 7.6% better area than those obtained using traditional CSE and algebraic decomposition.
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski,
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon
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