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SBACPAD
2009
IEEE

SPARC16: A New Compression Approach for the SPARC Architecture

13 years 10 months ago
SPARC16: A New Compression Approach for the SPARC Architecture
RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. Alternative encodings for instruction sets, such as MIPS16 and Thumb, represent an effective approach to deal with this drawback. This article proposes to apply a new encoding to the SPARCv8 architecture. Through extensive analysis of a program mix from the Mibench and Mediabench benchmark suites, we suggest a new 16-bit instruction set, easily translated to its 32-bit counterpart during execution time. Using the aforementioned program mix to infer how code could be represented in the proposed 16-bit ISA, compression ratios as low as 56% can be obtained. We also evaluated the cache behavior and showed reductions of 42% on cache misses that can increase performance up to 28% (for patricia program with 2KB cache).
Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo C
Added 21 May 2010
Updated 21 May 2010
Type Conference
Year 2009
Where sbacpad
Authors Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo Candido Xavier, Ricardo Pannain, Paulo Centoducatte, Rodolfo Jardim de Azevedo
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