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ISCAS
2007
IEEE

A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method

9 years 5 months ago
A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method
—The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the QuasiLinear interpolation (QLIP) method. The four-segment QLIP is utilized to realize a DDFS with a spurious free dynamic range (SFDR) of 63.2dBc. The DDFS chip featuring a 5-stage pipeline is implemented in TSMC 0.13μm technology. The chip occupies 9874μm2 , consumes 8.2μW/MHz, and runs at 1GHz clock rate.
Ashkan Ashrafi, Aleksandar Milenkovic, Reza R. Adh
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Ashkan Ashrafi, Aleksandar Milenkovic, Reza R. Adhami
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