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2011
IEEE

A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC

8 years 6 months ago
A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC
— A switched-capacitor single-stage sigma-delta ADC with a fifth-order modulator is proposed. The proposed sigmadelta ADC employs feed-forward architecture with oversampling ratio (OSR) of 8. The modulator input signal range is extended beyond the full scale of the quantizer with proper coefficients scaling and internal DAC reference scaling. A 19-level quantizer with data weighted averaging dynamic element matching (DWA DEM) technique is employed to improve the linearity of a multi-bit DAC. The prototype ADC fabricated in a 0.13-μm CMOS technology achieves 63.7 dB SNDR with 1 MHz input signal over 6.25 MHz signal bandwidth while consuming 52.5 mW with the clock frequency of 100 MHz.
Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-J
Added 21 Aug 2011
Updated 21 Aug 2011
Type Journal
Year 2011
Where ISCAS
Authors Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-Ju Kim, Kwang-Soo Kim, Seung-Hoon Lee, Gil-Cho Ahn
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