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DAC
2008
ACM

An 8x8 run-time reconfigurable FPGA embedded in a SoC

9 years 4 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. We explain the measures taken in the FPGA design to guarantee RTR functionality free of electrical conflicts, and we present a flow based on Altera synthesis tools to implement IPs(Hardware Blocks) in this FPGA. We demonstrate the full functionality with experiments on the FPGA, and as conclusion we highlight the limitations and future research directions. Categories and Subject Descriptors B.7.1 [ HARDWARE]: INTEGRATED CIRCUITS--Types and Design Styles, Gate arrays General Terms Design Keywords FPGA, RTR
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger
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