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HPCA
1995
IEEE

Access Ordering and Memory-Conscious Cache Utilization

12 years 3 months ago
Access Ordering and Memory-Conscious Cache Utilization
As processor speeds increase relative to memory speeds, memory bandwidth is rapidly becoming the limiting performance factor for many applications. Several approaches to bridging this performance gap have been suggested. This paper examines one approach, access ordering, and pushes its limits to determine bounds on memory performance. We present several access-ordering schemes, and compare their performance, developing analytic models and partially validating these with benchmark timings on the Intel i860XR.
Sally A. McKee, William A. Wulf
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where HPCA
Authors Sally A. McKee, William A. Wulf
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