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2006
ACM

An accurate and efficient simulation-based analysis for worst case interruption delay

11 years 5 months ago
An accurate and efficient simulation-based analysis for worst case interruption delay
This paper proposes an efficient method to analyze worst case interruption delay (WCID) of a workload running on modern microprocessors using a cycle accurate simulator (CAS). Our method is highly accurate because it simulates all possible cases inserting an interruption just before the retirement of every instruction executed in a workload. It is also (reasonably) efficient because it takes O(N log N) time for a workload with N executed instructions, instead of O(N2 ) of a straightforward iterative simulation of interrupted executions. The key idea for the efficiency is that a pair of executions with different interruption points has a set of durations in which they behave exactly coherent and thus one of simulations for the durations may be omitted. We implemented this method modifying the SimpleScalar tool set to prove it finds out WCID of workloads with five million executed instructions in reasonable time, less than 30 minutes, which would be 200
Hiroshi Nakashima, Masahiro Konishi, Takashi Nakad
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2006
Where CASES
Authors Hiroshi Nakashima, Masahiro Konishi, Takashi Nakada
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