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MICRO
2008
IEEE

Adaptive data compression for high-performance low-power on-chip networks

11 years 6 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communication. Much of the previous work has focused on router architectures and network topologies using wide/long channels. However, such solutions may result in a complicated router design and a high interconnect cost. In this paper, we exploit a table-based data compression technique, relying on value patterns in cache traffic. Compressing a large packet into a small one can increase the effective bandwidth of routers and links, while saving power due to reduced operations. The main challenges are providing a scalable implementation of tables and minimizing overhead of the compression latency. First, we propose a shared table scheme that needs one encoding and one decoding tables for each processing element, and a management protocol that does not require in-order delivery. Next, we present streamlined encoding th...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
Added 31 May 2010
Updated 31 May 2010
Type Conference
Year 2008
Where MICRO
Authors Yuho Jin, Ki Hwan Yum, Eun Jung Kim
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