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2007
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Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors

9 years 9 months ago
Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors
Energy-efficient microprocessor designs are one of the major concerns in both high performance and embedded processor domains. Furthermore, as process technology advances toward deep submicron, static power dissipation becomes a new challenge to address, especially for large on-chip array structures such as caches or prediction tables. Value prediction emerged in the recent past as a very effective way of increasing processor performance by overcoming data dependences. The more accurate the value predictor is the more performance is obtained, at the expense of becoming a source of power consumption and a thermal hot spot, and therefore increasing its leakage. Recent techniques, aimed at reducing the leakage power of array structures such as caches, either switch off (non-state preserving) or reduce the voltage level (statepreserving) of unused array portions. In this paper we propose the design of leakage-efficient value predictors by applying adaptive decay techniques in order to dis...
Juan M. Cebrian, Juan L. Aragón, José
Added 12 Aug 2010
Updated 12 Aug 2010
Type Conference
Year 2007
Where CF
Authors Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras
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