Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units

The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand values. The presented schemes focus on reducing the power at peak performance, where each FPU stage is used in nearly every cycle and conventional schemes have little impact on the power comsumption. Depending on the instruction mix, the schemes allow to turn off 18% to 74% of the register bits. Even for the worst case instruction 18% to 37% of the FPU are shut down depending on the data patterns.

• Type: Conference
• Year: 2009
• Where: ARITH
• Authors: Jochen Preiss, Maarten Boersma, Silvia Melitta Müller
• Keywords: Applied Computing, ARITH 2009, FPU Stage, Presented Schemes, fine-grain Clockgating Schemes