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2000
ACM

Algorithmic foundations for a parallel vector access memory system

11 years 4 months ago
Algorithmic foundations for a parallel vector access memory system
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access patterns. The Parallel Vector Access (PVA) unit exploits the regularity of vectors or streams to access them efficiently in parallel on a multibank SDRAM memory system. The PVA unit performs scatter/gather operations so that only the elements accessed by the application are transmitted across the system bus. Vector operations are broadcast in parallel to all memory banks, each of which implements an efficient algorithm to determine which vector elements it holds. Earlier performance evaluations have demonstrated that our PVA implementation loads elements up to 32.8 times faster than a conventional memory system and 3.3 times faster than a pipelined vector unit, without hurting the performance of normal cache-line fills. Here we present the underlying PVA algorithms for both word interleaved and...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al
Added 01 Aug 2010
Updated 01 Aug 2010
Type Conference
Year 2000
Where SPAA
Authors Binu K. Mathew, Sally A. McKee, John B. Carter, Al Davis
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