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DATE
2009
IEEE

Analysis and optimization of fault-tolerant embedded systems with hardened processors

9 years 3 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process re-execution in software to provide the required levels of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of re-executions in software. We present design optimization heuristics, to select the fault-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled.
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru
Added 16 Aug 2010
Updated 16 Aug 2010
Type Conference
Year 2009
Where DATE
Authors Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru Eles, Zebo Peng
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