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2007

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

10 years 1 months ago
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits
In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. We have analyzed the impact of resistive-opens placed in different locations of these circuits. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled by Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate...
Luigi Dilillo, Patrick Girard, Serge Pravossoudovi
Added 14 Dec 2010
Updated 14 Dec 2010
Type Journal
Year 2007
Where ET
Authors Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
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