Analysis of checksum-based execution schemes for pipelined processors

The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained easily but only with high additional power consumption. The electrical potential between logic ‘0’ and ‘1’ is decreased as integration and clock rates grow, leading to a higher susceptibility for transient faults, caused e.g. by power fluctuations or Single Event Upsets (SEUs). We introduce a technique which is based on the well-known cyclic redundancy check codes (CRCs) to secure the pipelined execution of common microprocessors against transient faults. This is done by computing signatures over the control signals of each pipeline stage including dynamic out-of-order scheduling. To correctly compute the checksums, we resolve the time-dependency of instructions in the pipeline. We will first discuss important physical properties of Single Event Upsets (SEUs). Then we present a model of a simple proc...

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Bernhard Fechner
• Keywords: Distributed And Parallel Computing, IPPS 2006, Single Event Upsets, Transient Faults, Well-known Cyclic Redundancy