Sciweavers

Share
DAC
2001
ACM

Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects

10 years 2 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new optimization technique has been employed to analyze the impact of line inductance on the circuit behaviour and to illustrate the implications of technology scaling on wire inductance. It is shown that reduction in the driver capacitance and output resistance with scaling makes deep submicron (DSM) designs increasingly susceptible to inductance effects. Also, the impact of inductance variations on performance has been quantified. Additionally, the impact of the wire inductance on catastrophic logic failures and IC reliability issues have been analyzed.
Kaustav Banerjee, Amit Mehrotra
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2001
Where DAC
Authors Kaustav Banerjee, Amit Mehrotra
Comments (0)
books