Sciweavers

Share
ICPP
2002
IEEE

Analysis of Memory Hierarchy Performance of Block Data Layout

10 years 6 months ago
Analysis of Memory Hierarchy Performance of Block Data Layout
Recently, several experimental studies have been conducted on block data layout as a data transformation technique used in conjunction with tiling to improve cache performance. In this paper, we provide a theoretical analysis for the TLB and cache performance of block data layout. For standard matrix access patterns, we derive an asymptotic lower bound on the number of TLB misses for any data layout and show that block data layout achieves this bound. We show that block data layout improves TLB misses by a factor of O(B) compared with conventional data layouts, where B is the block size of block data layout. This reduction contributes to the improvement in memory hierarchy performance. Using our TLB and cache analysis, we also discuss the impact of block size on the overall memory hierarchy performance. These results are validated through simulations and experiments on state-of-the-art platforms.
Neungsoo Park, Bo Hong, Viktor K. Prasanna
Added 14 Jul 2010
Updated 14 Jul 2010
Type Conference
Year 2002
Where ICPP
Authors Neungsoo Park, Bo Hong, Viktor K. Prasanna
Comments (0)
books