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DATE
2010
IEEE

An analytical method for evaluating Network-on-Chip performance

12 years 7 months ago
An analytical method for evaluating Network-on-Chip performance
Today, due to the increasing demand for more and more complex applications in the consumer electronic market segment, Systems-on-Chip consist of many processing elements and become larger and larger. While on-chip system designers must be able to get fast and accurate communication performance analysis for such huge systems, the simulation-based approaches are not adequate anymore. Addressing the increasing need for early performance evaluation in NoC-based system design flow, this paper presents a generic analytical method to estimate communication latencies and link-buffer utilizations for a given NoC architecture with a given application mapped on it. The accuracy of our method is experimentally compared with the results obtained from Cycle-Accurate SystemC simulations.
Sahar Foroutan, Yvain Thonnart, Richard Hersemeule
Added 10 Jul 2010
Updated 10 Jul 2010
Type Conference
Year 2010
Where DATE
Authors Sahar Foroutan, Yvain Thonnart, Richard Hersemeule, Ahmed Jerraya
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