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CASES
2011
ACM

Architecting processors to allow voltage/reliability tradeoffs

7 years 6 months ago
Architecting processors to allow voltage/reliability tradeoffs
Escalating variations in modern CMOS designs have become a threat to Moore’s law. While previous works have proposed techniques for tolerating variations by trading reliability for reduced voltage (energy) [10], the benefits of such techniques are limited, because voltage/reliability tradeoffs in conventional processors often introduce more errors than can be gainfully tolerated [14]. Recent work has proposed circuit and design-level optimizations [14, 15] that manipulate the error rate behavior of a design to increase the potential for energy savings from voltage/reliability tradeoffs. In this paper, we investigate whether architectural optimizations can also manipulate error rate behavior to significantly increase the energy savings from voltage/reliability tradeoffs. To this end, we demonstrate how error rate behavior indeed depends on processor architecture, and that architectural optimizations can be used to manipulate the error rate behavior of a processor. We show that a...
John Sartori, Rakesh Kumar
Added 13 Dec 2011
Updated 13 Dec 2011
Type Journal
Year 2011
Where CASES
Authors John Sartori, Rakesh Kumar
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