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2004
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An Architectural Framework for Providing Reliability and Security Support

10 years 2 months ago
An Architectural Framework for Providing Reliability and Security Support
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE), which is implemented as an integral part of a modern microprocessor. The RSE interacts with the processor through an input/output interface. The CHECK instruction, a special extension of the instruction set architecture of the processor is the interface of the application with the RSE. The detection mechanisms described here in detail are: (1) the Memory Layout Randomization (MLR) Module, which randomizes the memory layout of a process in order to foil attackers who assume a fixed system layout, thus protecting against many security threats, (2) the Data Dependency Tracking (DDT) Module, which tracks the dependencies among threads of a process and maintains checkpoints of shared memory pages in order to rollback the threads when an offending (potentially malicious) thread is terminated, (3) the Instruction ...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K.
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where DSN
Authors Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. Iyer, Jun Xu
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