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2003
ACM

Architectural optimizations for low-power, real-time speech recognition

10 years 9 months ago
Architectural optimizations for low-power, real-time speech recognition
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular interest in speech recognition. The computational demands of robust, large vocabulary speech recognition systems, however, are currently prohibitive for such low power devices. This work begins an exploration of domain specific characteristics of speech recognition that might be exploited to achieve the requisite performance within the power constraints of such devices. We focus primarily on architectural techniques to exploit the massive amounts of potential thread level parallelism apparent in this application domain, and consider the performance / power trade-offs of such architectures. Our results show that a simple, multi-threaded, multi-pipelined processor architecture can significantly improve the performance of the timeconsuming search phase of modern speech recognition algorithms, and may reduce overal...
Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
Added 05 Jul 2010
Updated 05 Jul 2010
Type Conference
Year 2003
Where CASES
Authors Rajeev Krishna, Scott A. Mahlke, Todd M. Austin
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