Architectural support for scalable speculative parallelization in shared-memory multiprocessors

Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs relatively simple hardware and is efficiently integrated into a cache-coherent NUMA system. We have designed the scheme in a hierarchical hat largely abstracts away the internals of the node. We effectively utilize a speculative CMP as the building block for our scheme. Simulations show that the architecture proposed delivers good speedups at a modest hardware cost. For a set of important nonanalyzable scientific loops, we report average speedups of 4.2 for 16 processors. We show that support for ...

• Type: Conference
• Year: 2000
• Where: ISCA
• Authors: Marcelo H. Cintra, José F. Martínez, Josep Torrellas
• Keywords: Hardware, Hardware Scheme, ISCA 2000, Scalable Speculative Parallelization, Speculative Parallelization