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1993
IEEE

Architectural Support for Translation Table Management in Large Address Space Machines

11 years 9 months ago
Architectural Support for Translation Table Management in Large Address Space Machines
Virtual memoy page translation tables provide mappings from virtual to physical addresses. When the hardware controlled Tratmlation L.ookaside Buffers (TLBs) do not contain a translation, these tables provide the translation. Approaches to the structure and management of these tables vary from full hardware implementations to complete software based algon”thms. The size of the virtual aaliress space used by processes is rapidly growing beyond 32 bits of address. As the utilized address space increases, new problems and issues surjace. Traditional methoak for managing the page translation tables are inappropriate for large address space architectures. The Hashed Page Table (HPI’), described here, provides a very fast and space ejicient translation table that reduces ovdwad by splitting TLB management responsibilities between hardware and software. Measurements demonstrate its applicability to a diverse range of operating systems and workloads and, in particular, to large virtual ad...
Jerome C. Huck, Jim Hays
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1993
Where ISCA
Authors Jerome C. Huck, Jim Hays
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