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ISCA
1999
IEEE

Area Efficient Architectures for Information Integrity in Cache Memories

13 years 8 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it difficult to trade between the level of data integrity and the chip area requirement. We focus on transient fault tolerance in primary cache memories and develop new architectural solutions to maximize fault coverage when the budgeted silicon area is not sufficient for the conventional configuration of an error checking code. The underlying idea is to exploit the corollary of reference locality in the organization and management of the code. A higher protection priority is dynamically assigned to the portions of the cache that are more error-prone and have a higher probability of access. The error-prone likelihood prediction is based on the access frequency. We evaluate the effectiveness of the proposed schemes using a trace-driven simulation combined with software error injection using four different fault ...
Seongwoo Kim, Arun K. Somani
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ISCA
Authors Seongwoo Kim, Arun K. Somani
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