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DAC
2008
ACM

An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing

9 years 11 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and low latency at relatively high area cost.In this paper, we introduce a hybrid MoT-BF network that combines MoT network with the area efficient butterfly network. We prove that the hybrid network reduces MoT network's area cost. Cycle-accurate simulation and post-layout results all show that significant area reduction can be achieved with negligible performance degradation, when operating at same clock rate. Categories and Subject Descriptors B.4.3 [Interconnections (Subsystems)]: Topology; C.2.1 [Network Architecture and Design]: Packet-switching Networks General Terms Design, Performance Keywords On-chip networks, Mesh-of-Trees, Hybrid networks
Aydin O. Balkan, Gang Qu, Uzi Vishkin
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Aydin O. Balkan, Gang Qu, Uzi Vishkin
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