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ICCD
2001
IEEE

An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking

10 years 16 days ago
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a multiplication. The partial CSA array is controlled by a fast internal clock generated using a selftimed technique. Compared with the array implementation, the proposed multiplier yields an 86.6% area reduction at the expense of 18.8% slow down for 64×64-bit multiplication.
Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2001
Where ICCD
Authors Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
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