Sciweavers

DATE
2005
IEEE

Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

13 years 9 months ago
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction
This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.
Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami,
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where DATE
Authors Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa
Comments (0)