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ASYNC
2007
IEEE

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

10 years 7 months ago
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous toolflows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal al
Tiberiu Chelcea, Girish Venkataramani, Seth Copen
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where ASYNC
Authors Tiberiu Chelcea, Girish Venkataramani, Seth Copen Goldstein
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