Sciweavers

Share
EVOW
2001
Springer

ARPIA: A High-Level Evolutionary Test Signal Generator

9 years 7 months ago
ARPIA: A High-Level Evolutionary Test Signal Generator
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones. 1 Background In recent years the application specific integrated circuit (ASIC) design flow experienced radical changes. Deep sub-m...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda
Added 28 Jul 2010
Updated 28 Jul 2010
Type Conference
Year 2001
Where EVOW
Authors Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero
Comments (0)
books