Sciweavers

Share
ISVLSI
2007
IEEE

Asymmetrically Banked Value-Aware Register Files

10 years 9 months ago
Asymmetrically Banked Value-Aware Register Files
Designing high-performance low-power register files is of critical importance to the continuation of current performance advances in wide-issue and deeply-pipelined superscalar microprocessors. In this paper, we propose a new microarchitecture, the asymmetrically-banked value-aware register file (AB-VARF), to exploit the prevailing narrowwidth register values for low-latency and power-efficient register file designs. The register bit-widths of different banks in our AB-VARF register files are specifically customized to capture different narrow-width values. Augmented with a value width predictor, the register renaming logic is slightly tuned to rename predicted narrow-width registers to the corresponding narrow-width banks. Our experimental evaluation with SPEC CINT2000 benchmark suites shows that AB-VARF reduces the energy consumption by 92.6% over a conventional register file, on the average, at the cost of a 6.6% performance loss to an ideal 1-cycle monolithic register file...
Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziav
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISVLSI
Authors Shuai Wang, Hongyan Yang, Jie Hu, Sotirios G. Ziavras
Comments (0)
books