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2005
IEEE

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow

9 years 4 months ago
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem. Creating a low skew clock tree for synchronous inter-block pipeline stages is a significant challenge. Asynchronous interconnect does not require a global clock and therefore it has a potential advantage in terms of design effort. This paper presents an asynchronous interconnect design that can be implemented using a standard ASIC flow. This design is considered in the context of a simple interconnect network. The results demonstrate that there is a region of the design space where the implementation provides an advantage over a synchronous interconnect. A detailed comparison of power, area and latency of the two strategies is also provided for a range of IC scenarios.
Bradley R. Quinton, Mark R. Greenstreet, Steven J.
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2005
Where ICCD
Authors Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton
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