Automated data cache placement for embedded VLIW ASIPs

Memory bandwidth issues present a formidable bottleneck to accelerating embedded applications, particularly data bandwidth for multiple-issue VLIW processors. Providing an efficient ASIP data cache solution requires that the cache design be tailored to the target application. Multiple caches or caches with multiple ports allow simultaneous parallel access to data, alleviating the bandwidth problem if data is placed effectively. We present a solution that greatly simplifies the creation of targeted caches and automates the process of explicitly allocating individual memory access to caches and banks. The effectiveness of our solution is demonstrated with experimental results. Categories and Subject Descriptors B.3.2 [Memory Structures]: Design Styles – Cache memories;

• Type: Conference
• Year: 2005
• Where: CODES
• Authors: Paul Morgan, Richard Taylor, Japheth Hossell, George Bruce, Barry O'Rourke
• Keywords: CODES 2005, Data Cache Solution, Memory Bandwidth Issues, Multiple Caches, Software Engineering