Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs

This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGAs) and a tool called PARBIT, it is possible to extract a partial bitstream containing a modular component developed on one Virtex FPGA that can be placed or relocated inside another Virtex FPGAs. The methodology to obtain the BIP cores is explained, along with details about PARBIT and Virtex devices.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Edson L. Horta, John W. Lockwood
• Keywords: Bitstream Intellectual Property, FPL 2004, Programmable Gate Arrays, Virtex Fpgas