Automatic Constraint Based Test Generation for Behavioral HDL Models

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The proposed work involves conversion of a given circuit model into a set of constraints and employing constraint solvers to generate tests for it. The method is demonstrated for the 16-bit DLX-architecture.

Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda

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Circuit Model | TVLSI 2008 |

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Added	16 Dec 2010
Updated	16 Dec 2010
Type	Journal
Year	2008
Where	TVLSI
Authors	Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil

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Automatic Constraint Based Test Generation for Behavioral HDL Models

Circuit Model | TVLSI 2008 |

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