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SAMOS
2005
Springer

Automatic FIR Filter Generation for FPGAs

12 years 7 months ago
Automatic FIR Filter Generation for FPGAs
This paper presents a new tool for the automatic generation of highly parallelized Finite Impulse Response (FIR) filters. In this approach we follow our PARO design methodology. PARO is a design system project for modeling, transformation, optimization, and synthesis of massively parallel VLSI architectures. The FIR filter generator employs during the design flow the following advanced transformations, (a) hierarchical partitioning in order to balance the amount of local memory with external communication, and (b), partial localization to achieve higher throughput and smaller latencies. Furthermore, our filter generator allows for design space exploration to tackle trade-offs in cost and speed. Finally, synthesizable VHDL code is generated and mapped to an FPGA, the results are compared with a commercial filter generator.
Holger Ruckdeschel, Hritam Dutta, Frank Hannig, J&
Added 28 Jun 2010
Updated 28 Jun 2010
Type Conference
Year 2005
Where SAMOS
Authors Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich
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