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DAC
2008
ACM

Automatic synthesis of clock gating logic with controlled netlist perturbation

9 years 4 months ago
Automatic synthesis of clock gating logic with controlled netlist perturbation
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids General Terms Algorithms, Design. Keywords Clock Gating, Lo...
Aaron P. Hurst
Added 12 Nov 2009
Updated 12 Nov 2009
Type Conference
Year 2008
Where DAC
Authors Aaron P. Hurst
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