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2004
IEEE

Automatic synthesis of system on chip multiprocessor architectures for process networks

9 years 1 months ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is targeted towards design space exploration (DSE) and thus the speed of synthesis is of critical interest. The focus here is on the problem of resource allocation and binding with a view to optimize cost under performance constraints. Our approach exploits adjacency relation of processes and uses a dynamic programming based algorithm to synthesize the architecture including interconnection network. We have done a number of experiments on real as well as randomly generated process networks. The results have been compared with an optimal MILP formulation. They conclusively show that this approach is fast as well as effective and can be employed for DSE. Categories and Subject Descriptors
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna
Added 20 Aug 2010
Updated 20 Aug 2010
Type Conference
Year 2004
Where CODES
Authors Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan
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