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DATE
2000
IEEE

Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience

10 years 2 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design productivity is greatly enhanced. However, in the new design flow, validation still remains a challenge: while new technologies based on formal verification are only marginally accepted, standard techniques based on simulation are beginning to fall behind the increased circuit complexity. This paper proposes a new approach to simulation-based validation, in which a Genetic Algorithm helps the designer in generating useful input sequences to be included in the test bench. The technique has been applied to an industrial circuit, showing that the quality of the validation process is increased.
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill
Added 30 Jul 2010
Updated 30 Jul 2010
Type Conference
Year 2000
Where DATE
Authors Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti
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