Automatic trace analysis for logic of constraints

Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present algorithms to automatically generate trace checkers from formulas written in the formal quantitative constraint language, Logic Of Constraints (LOC), to analyze the simulation traces for functional and performance constraint violations. For many interesting formulas, the checkers exhibit linear time complexity and constant memory usage. We illustrate the usefulness and efficiency of this approach with large designs and traces. Categories and Subject Descriptors B.8.2 [Performance and Reliability]: Performance Analysis and Design Aids; D.2.4 [Software Engineering]: Software/Program Verification--Assertion checkers General Terms Verification Keywords Performance constraint, Trace analysis, Logic of Constraints, Simulation checker

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
• Keywords: DAC 2003, Design Automation, Formal Quantitative Constraint, Keywords Performance Constraint, Performance Constraint Violations