Automating the Layout of Reconfigurable Subsystems via Template Reduction

When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such devices provides an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post -fabrication modification of circuits. To automate the layout of reconfigurable subsystems for systems-ona-chip, we present template reduction. Template reduction enables a designer to eliminate resources from a template that are unnecessary to support the specified applic ation domain. To facilitate this, we have created a feature rich template, from which we automatically generate application specific reconfigurable circuits. Compared to the full template, we achieve designs that are 53.4% smaller and 13.9% faster, while continuing to support the algorithms in a particular application domain.

• Type: Conference
• Year: 2004
• Where: FPL
• Authors: Shawn Phillips, Akshay Sharma, Scott Hauck
• Keywords: Application Domain, Feature Rich Template, FPL 2004, Template Reduction