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FCCM
2008
IEEE

Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration

10 years 5 months ago
Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration
This paper presents a proto-type autonomous signal processing system on a chip. The system is architected such that high performance digital signal processing occurs in the FPGA’s configurable logic, while resulting higher level data products are monitored by cognitive algorithms residing on an embedded processor. The cognitive algorithms develop situational awareness about the platform’s environment, and use this information to modify and tune signal processing in real-time using active partial reconfiguration. This system was realized on a Xilinx Virtex4 FX 100 device on a pulse parameter measurement application utilizing a Bayesian Network cognitive algorithm. Changes in the RF environment were correctly detected 96.7% of the time and mitigation filters which resulted in at least 3dB interference rejection improvement were instanced 81% of the time. This system
Matthew French, Erik Anderson, Dong-In Kang
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where FCCM
Authors Matthew French, Erik Anderson, Dong-In Kang
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