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2008
IEEE

Backlog Aware Scheduling for Large Buffered Crossbar Switches

8 years 9 months ago
Backlog Aware Scheduling for Large Buffered Crossbar Switches
—A novel architecture was proposed in [1] to address scalability issues in large, high speed packet switches. The architecture proposed in [1], namely OBIG (output buffers with input groups), distributes the switch fabric across multiple chips, which communicate via high speed interconnects enabled by proximity communication (PC) a recent circuit technology [2]. An OBIG switch aggregates multiple input flows inside the switch fabric, thereby significantly reducing the amount of memory required for internal buffers, vis-`a-vis a conventional buffered crossbar, which has buffers at every crosspoint. Thus, the OBIG architecture is promising for realizing terabit switches with hundreds of ports. In this paper, we study packet scheduling algorithms which help realize the potential of OBIG-like switch architectures. Our emphasis here is on designing backlog aware scheduling algorithms, while ensuring desirable traits such as low computational complexity and scalability. We demonstrate th...
Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wlad
Added 30 May 2010
Updated 30 May 2010
Type Conference
Year 2008
Where ICC
Authors Aditya Dua, Benjamin Yolken, Nicholas Bambos, Wladek Olesinski, Hans Eberle, Nils Gura
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