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2003
IEEE

Banked Multiported Register Files for High-Frequency Superscalar Microprocessors

9 years 7 months ago
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors
Multiported register files are a critical component of high-performance superscalar microprocessors. Conventional multiported structures can consume significant power and die area. We examine the designs of banked multiported register files that employ multiple interleaved banks of fewer ported register cells to reduce power and area. Banked register files designs have been shown to provide sufficient bandwidth for a superscalar machine, but previous designs had complex control structures that would likely limit cycle time and add to design complexity. We develop a banked register file with much simpler and faster control logic while only slightly increasing the number of ports per bank. We present area, delay, and energy numbers extracted from layouts of the banked register file. For a four-issue superscalar processor, we show that we can reduce area by a factor of three, access time by 25%, and energy by 40%, while decreasing IPC by less than 5%.
Jessica H. Tseng, Krste Asanovic
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISCA
Authors Jessica H. Tseng, Krste Asanovic
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