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EMSOFT
2004
Springer

Binary translation to improve energy efficiency through post-pass register re-allocation

9 years 4 months ago
Binary translation to improve energy efficiency through post-pass register re-allocation
Energy efficiency is rapidly becoming a first class optimization parameter for modern systems. Caches are critical to the overall performance and thus, modern processors (both high and low-end) tend to deploy a cache with large size and high degree of associativity. Due a large size cache power takes up a significant percentage of total system power. One important way to reduce cache power consumption is to reduce the dynamic activities in the cache by reducing the dynamic load-store counts. In this work, we focus on programs that are only available as binaries which need to be improved for energy efficiency. For adapting these programs for energy-constrained devices, we propose a feed-back directed post-pass solution that tries to do register re-allocation to reduce dynamic load/store counts and to improve energyefficiency. Our approach is based on zero knowledge of original code generator or compiler and performs a post-pass register allocation to get a more power-efficient binary. ...
Kun Zhang, Tao Zhang, Santosh Pande
Added 01 Jul 2010
Updated 01 Jul 2010
Type Conference
Year 2004
Where EMSOFT
Authors Kun Zhang, Tao Zhang, Santosh Pande
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