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8

DATE
2000
IEEE

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A BIST Scheme for On-Chip ADC and DAC Testing

13 years 8 months ago

A BIST Scheme for On-Chip ADC and DAC Testing

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In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measuring the DNL and INL of the converters. We validate the scheme with software simulation—5% LSB (least significant bit) test accuracy can be achieved in the presence of reasonable analog imperfection.

Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng

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DATE 2000 | Hardware | Least Significant Bit | Reasonable Analog Imperfection | Testing Onchip Ad |

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Added	30 Jul 2010
Updated	30 Jul 2010
Type	Conference
Year	2000
Where	DATE
Authors	Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng

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