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DAC
1996
ACM

Bit-Level Analysis of an SRT Divider Circuit

13 years 7 months ago
Bit-Level Analysis of an SRT Divider Circuit
Abstract-- It is impractical to verify multiplier or divider circuits entirely at the bit-level using ordered Binary Decision Diagrams (BDDs), because the BDD representations for these functions grow exponentially with the word size. It is possible, however, to analyze individual stages of these circuits using BDDs. Such analysis can be helpful when implementing complex arithmetic algorithms. As a demonstration, we showthat Intel could haveused BDDs to detect erroneous lookup table entries in the Pentium(TM) floating point divider. Going beyond verification, we show that bit-level analysis can be used to generate a correct version of the table.
Randal E. Bryant
Added 08 Aug 2010
Updated 08 Aug 2010
Type Conference
Year 1996
Where DAC
Authors Randal E. Bryant
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