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6

ASPDAC
2010
ACM

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Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

13 years 2 months ago

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization

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Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-W

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Added	10 Feb 2011
Updated	10 Feb 2011
Type	Journal
Year	2010
Where	ASPDAC
Authors	Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho, Yao-Wen Chang

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