Building heterogeneous reconfigurable systems using threads

Field Programmable Gate Arrays (FPGAs) have long held the promise of allowing designers to create systems with performance levels close to custom circuits but with a software-like productivity for reconfiguring the gates. Unfortunately achieving this promise has been elusive. Modern FPGAs can now support a complete Multi-processor System on Chip (MPSoC) architecture that raises the design abstraction level from gates to processors. In this paper we present a new design flow and run-time system that enables developers to create a complete heterogeneous MPSoC from high-level programel abstractions. This approach allows designers to eliminate synthesis times by using soft core processors thus enabling the creation of custom heterogeneous MPSoC architectures at software productivity levels.

• Type: Conference
• Year: 2009
• Where: FPL
• Authors: Jason Agron, David L. Andrews
• Keywords: Complete Heterogeneous Mpsoc, FPL 2009, Hardware, Heterogeneous Mpsoc, Programmable Gate Arrays